System Integration Senior Manager

● SOC Integration (IP Connectivity, IP Configuration, Bus Protocol Design etc)

● Subsystem Integration (PCIe, DDR, USB etc)

● Integrate controller and PHY at RTL level

● Integrate controller and PHY IP level SDC and generate subsystem level SDC

● Pass SOC, subsystem simulation

● Pass RTL QA items such as CDC, Lint, SDC validation

● Perform Synthesis (RTL to Netlist)

● Pass QA items such as LEC, STA, In-house Design Kit

● Generate HDM model (subsystem CDC model, for SOC level CDC)

● Generate subsystem document & database package

● Project Management and provide weekly progress update to Customers

● Familiar with System Verilog

● Familiar with Front-end EDA tools - Logic simulation tool, Cadence Xcelium or Synopsys VCS - Synopsys Design Compiler, PrimeTime, Lint - LEC tool, Cadence Conformal or Synopsys Formality - Clock Domain Crossing (CDC) tool, Synopsys SpyGlass or Mentor Graphic Questa CDC

● Familiar with PCIe Gen-4 spec

● Familiar with AMBA AXI, AHB, APB spec

● BS or MS degree in EE or CS related

● Good English communication skills

● Experience in UVM is a plus

● Min 2 years working experience

● Candidate with 8 years experience or more will be considered for technical lead position ● Candidate with lesser experience will be considered for junior position.

- Attractive salary, allowance and bonus with annual revision.

- Strong team spirit in an entrepreneurial environment of a growing company.

- People values, social responsibility, and sustainability.

- Intensive training on the job.

- Opportunities for self-development and career advancement