SOC Physical Design Engineer (Experienced)

● ASIC physical implementation by using automatic place and route tools

● Floor planning, powerplan synthesis, clock tree synthesis, timing closure, routing, and post-route optimization

● Physical verification signoff including DRC, LVS, ERC, Antenna and ESD

● Coordinate cross-site communication and coordination among internal supporting groups

● Familiar with Cadence Innovus or Synopsys Fusion Compiler flow

● Familiar with timing closure, IR drop analysis and physical verification

● Excellent team and interpersonal skills

● BS or MS degree in EE or CS related

● Good English communication skills

● Min 2 years working experience

● Candidate with 8 years experience or more will be considered for senior manger/technical lead position

● Candidate with lesser experience will be considered for junior position

- Attractive salary, allowance and bonus with annual revision.

- Strong team spirit in an entrepreneurial environment of a growing company.

- People values, social responsibility, and sustainability.

- Intensive training on the job.

- Opportunities for self-development and career advancement