Design & Verification Engineer

Input the specifications requested by the customer, and carry out specific design verification work using the following languages.

・Function specifications (English)

・Mounting specifications (English)

・RTL (Verilog/SystemVerilog) or high-level synthesis (SystemC/C/C++)

・Verification strategy (English)

・Verification item table (English)

・Verification environment construction/verification scenario (SystemVerilog/SVA/UVM/C)

・Verification environment manual (English)

・Verification result report (English)

＜Must＞

・+3 years experience for same position

・Skill for Verilog

＜Prefer＞

・Skill for System Verilog

・Skill for Synopsys or Cadence

・Raise in salary （April）

・Bonus 3 times （Summer, Winter, Tet bonus) ≒ 3 months bonus

・Position allowance

・IT Admin allowance（1,500,000VND/month）

・Lunch allowance（1,000,000VND/month）