Design Verification Engineer

ABOUT US
HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. Our technology products and services are built on four decades of innovation, with a world-renowned management philosophy, a strong culture of invention and risk-taking, and a relentless focus on customer relationships. HCL also takes pride in its many diversity, social responsibility, sustainability, and education initiatives. Through its worldwide network of R&D facilities and co-innovation labs, global delivery capabilities, and over 187,000+ ‘Ideapreneurs’ across 50 countries, HCL delivers holistic services across industry verticals to leading enterprises, including 250 of the Fortune 500 and 650 of the Global 2000.

Enterprises across industries stand at an inflection point today. In order to thrive in the digital age, technologies such as analytics, cloud, IoT, and automation occupy center stage. In order to offer enterprises the maximum benefit of these technologies to further their business objectives, HCL offers an integrated portfolio of products and services through three business units. These are IT and Business Services (ITBS), Engineering and R&D Services (ERS), and Products and Platforms (P&P).

Position: Verification/ Logic Design Engineer (Hanoi & HCMC)
Location: Ha Noi, Ho Chi Minh

RESPONSIBILITIES:

• To be responsible for managing technology in projects and providing technical guidance or solutions for work completion
• To be responsible for providing technical guidance or solutions
  To develop and guide the team members in enhancing their technical capabilities and increasing productivity
• To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.
• To ensure process compliance in the assigned module, and participate in technical discussions or review.

REQUIREMENTS:

• 3+ years of Experience.
• Bachelors/Masters degree in Electronics /Electrical Engineering with 5+ year’s experience in verification
• Good understanding of ASIC/SoC life cycle
• Experience in OVM/UVM methodologies using SV
• Experience with Full chip test plan development/modification
• Experience with Testbench development/modification , Test case development, coding, execution, bug analysis, Regressions, coverage analysis ,Verification closure
• Experience in prevalent standards & Protocols viz. PCIe Gen3/4/5/USB3/DDR4/5, /Ethernet / CSI2 / I3C / AMBA
• Experience with Gate level simulations
• Experience in scripting
• Should have participated in multiple ASIC/SoC verification till tape out stage